Student Task 15:
• Have a look at the VHDL code. Two binary inputs are compared to each other. If the first number is equal,
smaller, or larger than the second number, separate outputs are set accordingly.
• Now, synthesize the code and investigate the log, reports and resulting netlist. Note that while elaborating
the VHDL file, you have to set the parameter WIDTH : set it to 4 (Hint: elaborate <design_name> \
-parameters "<parameters> = XX").
• Are there some additional cells, which you had not intended?
• Correct the source code such as to prevent those cells from being inferred. After having changed the source
code, you have to perform an RTL simulation to verify the correct functionality of it. For that, we have already
prepared a testbench, which is located at ./sourcecode/comparator tb.vhd. For the simulation, you can use the
script located at ./modelsim/comparator compile rtl.csh
• Show your source code correction and the simulation results to an assistant.
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