Vision VHD-800 Spezifikationen

Institut f¨ur Integrierte SystemeIntegrated Systems LaboratoryDepartment of Information Technology and Electrical EngineeringVLSI I: From Architecture

Afterwards you can check whether your re-run was successful or not with the check_design command.Beside the SYNOPSYS DESIGN COMPILER commands you have

COUNT_DO[4]COUNT_DO[3]COUNT_DO[2]COUNT_DO[1]COUNT_DO[0]COUNT_DP_reg[3]COUNT_DP_reg[4]COUNT_DP_reg[2]COUNT_DP_reg[1]COUNT_DP_reg[0]RST_RBICLK_CIENA_SID

6 Example III: Constraining a CircuitIn this section, we will go through the synthesis process of a small design step by step and explore different co

6.2 Defining a Clock PeriodIn the above example, no constraints were given and the SYNOPSYS DESIGN COMPILER synthesized the design with theminimum poss

Student Task 6: Using the report_timing command determine the timing information of the circuit. Which of thetimings illustrated in Figure 7 gets actu

6.4 Input and Output TimingIn the following part we will examine the effect of the input and the output timing.Input Timing: It is clear that the outp

6.5 Setting Input Drivers and Output LoadInput Drivers: In the next steps we want to investigate how the driver that drives the inputs of our circuit

Student Task 13: Now, redo the compilation with the constraints listed in Table 2. Furthermore, keep the previouslydetermined input- and output-delays

Be aware of the fact that the compilation steps will take longer and longer. The compiler has to push all its efforts to thelimit for increasing const

8 Synthesis HintsThroughout this section, some useful hints with regard to synthesis will be given. They may help you during this exerciseor during on

1 IntroductionThe VLSI design flow is described in detail in the VLSI textbook. In Figure 1, a very rudimentary overview is given in orderto identify t

9 Commonly used Synopsys Design Compiler CommandsTable 4: A short cheatsheet for the Synopsys Design Compiler.Command DescriptionUser Interface Comman

cp /unspecified/shell.cmd .(a) Unspecified shell command.sh > cp /unix/shell.command .(b) Standard UNIX shell command.dvc > cp /this/is/a/design/

4 Example I: GUI Guided TrainingBasically, the SYNOPSYS DESIGN COMPILER tools can be subdivided into two major parts:Design Vision: This is the graphi

4.2 Design Vision - ConsoleThe Design Vision Console provides a facility to enter commands in textual form, this way linking the graphical user-interf

Note: Although the command compile is still known by the SYNOPSYS DESIGN COMPILER, it has been re-placed by compile_ultra. During this exercise, you m

• Open it using the less programa:sh > less crc4.vThe netlist contains a number of logic gates from the standard cell library, interconnected with

5 Example II: Getting to Grips with the Command LineIn the first exercise example you have learned what steps are necessary in order to synthesize a de

Student Task 2:• In the following, the first two commands of the synthesis script are listeda.remove_design -designssh rm -rf WORK/*• Add a short descr